Advanced Computer Architecture-II (V-U)

• History and Introduction (V-U)
• Growth in Processor Performance (V-U)
• I/O Performance, Concluding: Quantitative Principles (V-U)
• ISA Taxonomy, Memory Addressing Modes, Types of Operands, Types of Operations (V-U)
• Instruction Set Encoding, MIPS Instruction Set (V-U)
• DSP Media Operations, ISA Performance Putting it all Together (V-U)
• Basics of Computer Hardware Design, Single Cycle Design: Data Path Design, Control Design (V-U)
• Example of Single Cycle Design, Multi Cycle Design: Datapath (V-U)
• Key Components of Pipeline Datapath (V-U)
• Structural Hazards, Data Hazards, Control Hazards (V-U)
• Longer Pipelines - FP Instructions, Loop Level Parallelism, FP Loop Hazards (V-U)
• In-order Execution, Out-of-Order Execution, Scoreboard Technique (V-U)
• Tomasulo's Approach (V-U)
• Dynamic Branch Prediction, Branch Prediction Buffer (V-U)
• Correlating Branch Predictors, Tournament Predictor (V-U)
• Superscalar Processors (V-U)
• Hardware-based Speculations, Speculating on the Outcome of Branches (V-U)
• Limitations of ILP (V-U)
• Software Approaches to Exploit ILP (V-U)
• Static Multiple Issue: VLIW Approach, Detecting and Enhancing Loop Level Parallelism (V-U)
• Eliminating Dependent Computations, Software Pipelining, Trace Scheduling, Superblocks (V-U)
• H/W Support at Compile Time (V-U)
• H/W Support at Compile Time (Cont.), Speculation Mechanism: H/W Vs. S/W (V-U)
• Storage Technologies, RAM and Enhanced DRAM, Disk Storage (V-U)
• Concept of Cache Memory, Principle of Locality, Cache Addressing Techniques (V-U)