Digital Logic Design (V-U)

• Introduction & Overview to Digital Logic (V-U)
• Number Systems (V-U)
• Number Systems (contd.) (V-U)
• Number Systems & Codes (V-U)
• Digital Circuits and Operational Characteristics (V-U)
• Boolean Algebra and Logic Simplification (V-U)
• Boolean Algebra and Logic Simplification (contd.) (V-U)
• Karnaugh Map & Boolean Expression Simplification (V-U)
• Karnaugh Map & Boolean Expression Simplification (contd.) (V-U)
• Comparator (V-U)
• Odd-Prime Number Detector (V-U)
• Implementation of an Odd-Parity Generator Circuit (V-U)
• BCD Adder (V-U)
• 16-Bit ALU (V-U)
• The 74XX138 3-to-8 Decoder (V-U)
• Multiplexer (V-U)
• Demultiplexer (V-U)
• Implementing constant 0s and 1s (V-U)
• The GAL16V8 (V-U)
• ABEL input file of a Quad 1-of-4 MUX (V-U)
• Application of S-R Latch (V-U)
• Asynchronous Preset and Clear Inputs (V-U)
• The 555 Timer (V-U)
• Down Counters (V-U)
• Timing diagram of a Synchronous Decoder Counter (V-U)